The present invention relates to an arithmetic logic unit (ALU) such as a microprocessor or a digital signal processor (DSP) and, more particularly, to a processor having a circuit for generating a status signal of an arithmetic operation which is internally executed.
When binary addition/subtraction is performed, a conventional ALU directly uses sign bit Zs of arithmetic operation result Z as a sign flag representing the sign of arithmetic operation result Z.
Since an arithmetic operation is executed with a finite word length, an overflow carry may generate. If this overflow carry is generated, an adder outputs an incorrect arithmetic operation result, and a register which stores the arithmetic operation result also stores the incorrect sign flag.
This state (storage of the incorrect sign flag) can be avoided by detecting an overflow carry, and generating an overflow carry flag to indicate that the arithmetic operation result is incorrect.
This method, however, has the following two problems.
First, the arithmetic operation amount increases in an arithmetic operation which may generate an overflow carry because overflow carry detection must be executed every arithmetic operation. This typically occurs in a case requiring only the sigh of the arithmetic operation result. A descriptive example by the assembly language in this case is given as follows.